Blog / How to walk through the physical design flow in an interview

How to walk through the physical design flow in an interview

Physical Design · InterviewPS team · 30 October 2026
In short
Answer "walk me through the PD flow" as a chain of stages, each with what goes in, what you do and what you check before moving on: import, floorplan, power plan, placement, CTS, routing, timing closure, signoff and ECO. Keep each stage to two or three sentences. The interviewer will stop you at one of them, and the follow-up is where the interview is decided.

Why this question comes first

Most physical design interviews open with some version of "walk me through the flow". It is not a recall test. The interviewer is watching whether you know what each stage consumes and produces, and whether you can say what would make you stop and go back.
A common pattern is to let you talk for a minute, interrupt at a stage, and ask something specific. If you answer well they either go deeper on that stage or move you along. So prepare the flow as a spine with a few solid facts hanging off each stage, not as one long speech.

The stages, with one line on what to say

  • 1.
    Import: read the netlist, timing constraints (SDC), libraries and technology files, then sanity-check them. Unconstrained paths, missing library cells and clock definitions that do not match the design belong here.
  • 2.
    Floorplan: set die and core size and aspect ratio, place macros and I/O, and add placement blockages. Macro placement decides much of the later congestion and timing.
  • 3.
    Power plan: build the power and ground grid (rings, straps, rails) against an IR-drop target. Too sparse and you fail IR later; too dense and you steal routing tracks.
  • 4.
    Placement: place standard cells, watch congestion and timing, and reorder scan chains to shorten wiring.
  • 5.
    Clock tree synthesis: build the clock tree against skew and latency targets. Useful skew, where you deliberately skew a clock to help a critical path, is a common follow-up.
  • 6.
    Routing: global routing, track assignment, then detailed routing, and clean up DRC violations.
  • 7.
    Timing closure: fix setup and hold across corners and modes, with on-chip variation modelled by OCV, AOCV or POCV derates.
  • 8.
    Signoff: IR drop and electromigration, signal integrity and crosstalk, and physical verification (DRC, LVS, antenna).
  • 9.
    ECO: functional or timing changes late in the schedule, sometimes restricted to metal layers only.

Where interviewers usually stop you

Three stages draw most of the follow-ups, because they show judgement rather than vocabulary.
  • •
    Floorplan: "How do you decide where the macros go?" Talk about data flow between macros and logic, keeping channels wide enough to route, and placing macros toward the edges so the core stays open for standard cells.
  • •
    CTS: "Why not aim for zero skew?" Zero skew is not the goal in itself; what matters is that setup and hold close. Useful skew can borrow time for a critical path, at the cost of the paths around it.
  • •
    Timing closure: "Setup is fixed but hold broke. What happened?" Fixes that speed up data paths or shift clock arrival can create hold violations, and hold must be met at the fast corner, so you re-check every corner after each round of fixes.
When you are stopped, answer the question asked, then add one sentence on the trade-off. That sentence is what separates a mid-level answer from a senior one.

What changes with seniority

A junior candidate is expected to name the stages in order and define the terms correctly. A mid-level candidate should explain how they would handle a problem at a stage, such as congestion after placement. A senior candidate is expected to talk about trade-offs across stages, for example accepting a larger die to protect the schedule, or pushing back on a floorplan that cannot close. At expert level the questions are open-ended, and the interviewer pushes on your reasoning more than on any one fact.

Mistakes that cost candidates the question

  • •
    Listing stage names without saying what each one checks. The interviewer learns nothing from a list.
  • •
    Treating the flow as one-way. Real flows loop back: a congestion problem after placement can send you back to the floorplan.
  • •
    Quoting numbers from a specific process node or tool as if they were universal. Say which node or library you mean, or speak about the method.
  • •
    Going too deep on the first stage and never reaching timing closure, which is often where the interviewer wanted to go.

How to practise it

Say the flow out loud in under two minutes, one or two sentences per stage. Then pick any stage and answer three follow-ups about it without notes. On InterviewPS the flow is drawn as a row of stages, and each stage opens the questions asked at that point, so you can practise exactly where the interruption lands.

Sources

  • A. B. Kahng, J. Lienig, I. L. Markov, J. Hu, VLSI Physical Design: From Graph Partitioning to Timing Closure, 2nd ed., Springer, 2022
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